The present invention generally relates to methods of producing semiconductor devices using reactive ion etching (hereinafter simply referred to as RIE), and more particularly to a method of producing a semiconductor device using a predetermined gas which at least includes (Br.sub.2) gas as a reactive gas for the RIE, so as to improve the patterning accuracy.
Photolithography and electron beam lithography techniques are used for producing minute electronic circuits such as semiconductor parts including integrated circuits (ICs) and large scale integrated circuits (LSIs), and circuit parts including magnetic bubble memories and surface wave filters. When forming a circuit part on a substrate, metal and insulator layers are formed on the substrate by a vacuum deposition, a chemical vapor deposition and the like. A photoresist layer is formed on the metal and insulator layers on the substrate, and the photoresist layer is exposed by a projection exposure or a contact exposure. In the case where a positive photoresist is used for the photoresist layer, exposed portions of the photoresist layer are dissolved. On the other hand, in the case where a negative photoresist is used for the photoresist layer, non-exposed portions of the photoresist layer are dissolved. A pattern formed by the remaining photoresist layer is used as a mask to carry out a patterning process by an etching.
The etching can be divided into a wet etching which carries out the etching process chemically, and a dry etching which carries out the etching process physically. At first, the wet etching was preferred, but as the integration density of devices improved, the wet etching caused problems in that the so-called side etching phenomenon occurred due to the chemical etching. The side etching phenomenon is a phenomenon in which a side wall of a layer is etched in excess because there is no anisotropy in the chemical etching. For this reason, the dry etching, especially the RIE, is now popularly used since it is possible to carry out an anisotropic etching which does not cause the side etching phenomenon.
The RIE is carried out as follows. The substrate is placed on a cathode which is coupled to a radio frequency generator for generating a high frequency voltage of 13.56 MHz, for example. A glow discharge is generated inside an etching chamber so as to introduce a voltage drop in the cathode voltage in accordance with a difference in mobilities of ions and electrons in the plasma due to the glow discharge. The RIE uses positive ions in the gas plasma which hit the substrate on the cathode due to this voltage drop.
Conventionally, a halide such as carbon tetrafluoride (CF.sub.4), carbon tetrachloride (CCl.sub.4) and methane trifluoride (CHF.sub.3) is used as a reactive gas. The F.sup.+ and Cl.sup.+ ions in the plasma are highly reactive, and these ions react with the metal and insulator layers on the substrate to effect the etching. The positive ions of the halide react with the materials on the substrate and form a halide gas, but the dry etching progresses because the halide gas is easily evacuated out of the etching chamber due to the high vapor pressure.
As one example of the use of the RIE, there is the case where a wiring pattern is formed by the RIE. In this case, an aluminum (Al) layer is formed on a phospho-silicate glass (PSG) layer and over a contact hole in the PSG layer, and a photoresist layer is formed on the Al layer. The PSG layer is formed on a semiconductor substrate, and an impurity region is formed in the semiconductor substrate under the contact hole. The photoresist layer is patterned in accordance with the wiring pattern which s to be formed, and the wiring pattern of the Al layer is formed by the RIE using the photoresist layer as a mask. Ideally, the diameter of the contact hole and the width of the wiring pattern are equal to each other and the wiring pattern should be formed immediately over the contact hole. However, due to a positioning error which is inevitably introduced, the contact hole and the wiring pattern do not coincide and the photoresist layer may only cover a portion of the Al layer in the contact hole. Hence, when the conventional RIE is carried out by using the chlorine (Cl.sub.2) based reactive gas, the impurity region in the semiconductor substrate under the contact hole is easily etched and the etching may progress for the entire depth of the impurity region to thereby cause a short circuit. For this reason, the wiring pattern is conventionally formed with a certain margin, that is, the wiring pattern is dilated at the contact hole, so as to prevent such a short circuit. As a result, there is a problem in that the dilated wiring pattern prevents the improvement of the integration density of the semiconductor device.
There is also the case where a PSG layer is formed on a first Al layer, and a second A1 layer is formed on the PSG layer and over a contact hole in the PSG layer, and a photoresist layer is formed on the second Al layer. The photoresist layer is patterned in accordance with the wiring pattern which is to be formed, and the wiring pattern of the second Al layer is formed by the RIE using the photoresist layer as a mask. However, due to reasons similar to those described above, the first Al layer is easily etched and the etching may progress for the entire depth of the first Al layer when the conventional RIE is carried out by using the Cl.sub.2 based reactive gas.
In the LSIs and very large scale integrated circuits (VLSIs) having the metal oxide semiconductor (MOS) structure, polysilicon is used to form a gate electrode by self-alignment. The resistivity of polysilicon is reduced by controlling the doping and grain size of the impurity, but the limit of the reduction of the resistivity is approximately 500 .mu..OMEGA. cm. Hence, in order to improve the conductivity, a two-layer construction comprising the polysilicon layer and a metal of silicon and a refractory metal. As known metal silicides, there are titanium silicide (TiSi.sub.2) having a resistivity in the range of 13 .mu..OMEGA. cm to 16 .mu..OMEGA. cm, tungsten silicide (WSi.sub.2) having a resistivity in the order of 70 .mu..OMEGA. cm, and molybdenum silicide (MoSi.sub.2) having a resistivity in the order of 100 .mu..OMEGA. cm. These metal silicides have high melting temperature and high oxidation resistance, and have properties similar to those of silicon.
As another example of the use of the RIE, there is the case where the RIE is carried out a plurality of times when producing an erasable programmable read only memory (EPROM). A first polysilicon layer is formed on an oxide layer which is formed on a silicon (Si) substrate. Next, a silicon dioxide (SiO.sub.2) layer, a second polysilicon layer and metal silicide layer are successively formed on the first polysilicon layer. When forming a gate electrode, a photoresist layer is formed on the metal silicide layer and is then patterned, and the fluorine or chlorine based gas is used as the reactive gas to etch the metal silicide layer and the second polysilicon layer by the RIE. The difference between the etching rates of metal silicide and polysilicon is small, and the metal silicide layer and the second polysilicon layer can be etched satisfactorily. Thereafter, the reactive gas is changed to CHF.sub.3 to etch the SiO.sub.2 layer by the RIE, and the original reactive gas is used again to etch the first polysilicon layer so as to complete the formation of the gate electrode.
When forming the gate electrode, the photoresist layer must withstand the three selective etching processes, however, in actual practice, the photoresist layer cannot withstand all of the etching processes. As a result, there is a problem in that the dimensional accuracy and reliability of the gate electrode becomes poor due to the damaged photoresist layer.
Accordingly, there is a demand to realize a method of producing a semiconductor device using the RIE in which it is possible to improve the patterning accuracy and the integration density.